This invention relates to electrostatic discharge protection for electronic devices comprising arrays of pixels.
Electrostatic discharge (ESD) damage is a well known phenomenon which can occur during the fabrication of semiconductor devices, such as metal-oxide semiconductor (MOS) structures. In particular, ESD damage can result in gate insulating layer breakdown, large shifts in threshold voltages and large leakage currents between transistor electrodes.
ESD damage has been found to be a particular problem during the fabrication of devices using arrays of thin film transistors (TFTs), such as those serving as pixel switching elements in pixellated devices. Arrays of these transistors are used in, for example, active matrix liquid crystal displays and other active matrix display devices, and in sensing array devices such as radiation imaging detectors as well. During fabrication, significant quantities of charge may form on the source and drain electrodes of the TFTs. In particular, the row and column conductors used to address the individual pixels in the array provide long conductors on which static charge can be picked up and subsequently transferred to the TFT electrodes.
This static charge may result in breakdown of the gate insulating layer, and can result in a voltage differential between the gate and source electrodes or the gate and drain electrodes which can in turn cause the threshold voltage of the TFTs to shift.
The problem of ESD damage is not confined to TFT array devices but can be found also in array devices using alternative kinds of switching elements, for example two terminal devices such as thin film diodes or other non-linear devices.
The need to prevent ESD damage is widely recognised, and several different approaches have been developed. One example is the use of shorting bars surrounding the TFT array which link all of the source lines and gate lines of the individual TFTs together. The shorting lines are manufactured at the same time as the gate and source lines, so that the gate and source electrodes remain at the same potential throughout the fabrication process. This prevents any voltage differential from occurring across electrodes of the transistors, and therefore prevents ESD damage within the TFT devices.
However, the shorting lines must be removed from the device before the switching array can be used. This requires a cutting process, which is typically carried out after testing of the TFT switches, but before connection of the TFT array to peripheral circuitry. This introduces additional processing steps, and also means that the ESD protection is not available during the operation of connecting peripheral circuitry to the TFT array.
It is also known to provide ESD damage protection circuits which remain in place even during operation of the device. These circuits typically allow charge to flow between a common electrode and the row or column lines when a voltage differential is exceeded. A problem with these circuits is that they may consume a considerable proportion of the total power budget of the device. For example, in low power active matrix LCD applications, more than 50% of the total display power budget may be consumed by the protection circuits. Therefore, whilst these circuits may provide protection during fabrication of the TFT array and also during connection of peripheral circuitry, unacceptably high levels of power consumption may result during operation of the manufactured device.
According to the invention, there is provided an electronic device comprising:
an array of pixels provided on a substrate and arranged in rows and columns, each pixel comprising a switching element;
a plurality of row and column address lines for addressing each pixel;
wherein each row and column address line is connected to a first discharge element through a first discharge device and to a second discharge element through a second discharge device,
wherein the first discharge device allows the passage of charge between the address line and the first discharge element when the address line is at a potential below that of the first discharge element, and
the second discharge device allows the passage of charge between the address line and the second discharge element when the address line is at a potential above that of the second discharge element.
Each row and column is associated with two discharge elements, one of which is used to discharge electrostatic charges resulting in an increase in voltage on the row or column address line, and the other of which is used to discharge electrostatic charges resulting in a drop in the voltage on the row or column address line. By providing suitable voltages on the two discharge elements during operation of the manufactured device, it is possible to prevent the discharge devices from operating. In particular, during operation of the device, voltages may be provided on the discharge elements which result in all of the discharge devices being reverse-biased, for all normal operating voltages applied to the row and column address lines.
The first and second discharge elements may each comprise a conductive track to which all rows and columns are connected through a respective discharge device. The two tracks may then be arranged around the periphery of the pixel array.
Each discharge element may comprise at least one diode-connected transistor. During fabrication of the device, no external voltages are applied to the discharge elements, and any electrostatic charge resulting in a change in voltage sufficient to overcome the effective diode turn-on voltage will result in forward bias of the diode-connected transistor, so that charges can be dissipated to one or other of the discharge elements. However, during operation of the device, voltages are applied to the discharge elements so that the diode-connected transistors are always reverse-biased.
Preferably, therefore, the first discharge element is connected to a voltage supply line for supplying a first, lowest, voltage to the pixels, and the second discharge element is connected to a voltage supply line for supplying a second, highest, voltage to the pixels.
During fabrication of the device, it is preferable for the two discharge elements to be coupled together. This may be provided by a temporary short circuit between the first and second discharge elements, which may be broken before operation of the fabricated device. Alternatively, a diode ladder may be provided between the first and second discharge element. This diode ladder will have a sufficiently high resistance that when the supply voltages are applied to the discharge elements, a low power dissipation results even if the diode ladder is left in place during operation of the device.
As a further alternative, a protection circuit may be provided between the first and second discharge elements, the protection circuit providing first and second paths between the first and second discharge elements, each path having a transistor,
wherein with no external voltages applied to the first and second discharge elements, the first path provides electrostatic protection, and the transistor in the second path is turned off, and with external voltages applied to the first and second discharge elements, the transistor in the first path is turned off, and the transistor in the second path is turned on and provides a high impedance between the first and second discharge elements.
This protection circuit allows charges to flow between the two discharge elements when no external voltages are applied, but provides a much greater impedance between the two discharge elements when external voltages are applied, turning off the transistor in the first path. Again, the external voltages may comprise the lowest drive voltage required by the device (which is connected to the first discharge element), and the highest voltage required by the device (which is connected to the second discharge element).
In particular, the protection circuit may comprise a first path between the first and second discharge elements, comprising a first transistor,
a second path between the first and second discharge elements, comprising a second transistor and a resistor in series,
wherein the gate of the first transistor is connected to the junction between the resistor and the second transistor, and wherein the second transistor has a gate control line to enable it to be turned on or off.
This circuit is arranged such that with no signal applied to the gate control line, the second transistor is turned off, and when the second transistor is turned on, the voltage at the junction turns off the first transistor.
The device of the invention may typically comprise a liquid crystal display.
Although particularly useful in pixellated devices whose pixels include TFTs, the invention is applicable also to array devices using alternative kinds of switching elements such as two terminal non-linear devices, for example thin film diode elements.